Scalable Software Hardware computing Architecture Platform for Embedded Systems

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CastNess08 15-16-17-18 January 2008 Roma Workshop and school

CastNess07 15-17 January 2007 Roma Workshop and School

  • View the presentations delivered at CastNess07: Computer Architectures and Software Tools for Numerical Embedded Scalable Systems Workshop and School
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FET-ACA 2008 REVIEW: AETHER, SARC, SHAPES PROJECTS

Abstract

There is no processing power ceiling for the demand of low consumption, low cost, dense DSP for future embedded audio, video, human-centric applications. Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. The main problem is wiring, which threats Moore’s law. Future computing architectures for Embedded DSP and Control are strategic and deserve adequate research efforts. Tiled architectures suggest a possible HW path: “small” processing tiles connected by “short wires”.

Tiled Architectures will cover a significant share of 10+ year embedded applications. SHAPES will set a new density record with multi-Teraops single-board computers and multi-Petaops systems, and will be based on a groundbreaking HW/SW architecture paradigm. The heterogeneous SHAPES tile is composed of a VLIW floating-point DSP, a RISC, on chip memory, and a network interface. It includes a few million gates, for optimal balance among parallelism, local memory, and IP reuse on future technologies. The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbours toroidal engineering methodologies will be used for off-chip networking and maximum system density.

The SW challenge is to provide a simple and efficient programming environment. SHAPES will investigate a layered system software, which does not destroy algorithmic and distribution info provided by the programmer and is fully aware of the HW paradigm. For efficiency and Quality of Service, the system SW manages intra-tile and inter-tile latencies, bandwidths, computing resources, using static and dynamic profiling. The SW accesses the on-chip and off-chip networks through a homogeneous interface. The same HW and SW interface is adopted for integration with signal acquisition and reconfigurable logic tiles.

Hereafter the members and main roles of the partners of the SHAPES consortium:

  • ATMEL Roma (co-ordinating partner) RISC+VLIW Processing Tile;
  • ETH Zurich Distributed Operation Layer;
  • RWTH Aachen University Simulation of Multi Processor Systems;
  • TIMA Grenoble Laboratory and
  • THALES: Hardware Dependent Software Layer and OS;
  • TARGET Compiler Technologies: Retargetable VLIW Compilers;
  • STMicroelectronics, University of Cagliari and University of Pisa: Packet Switching Network on Chips;
  • INFN Roma: DNP (Distributed Network Processor) and 3D Dense System/Processor Eng. Methodology;
  • FRAUNHOFER IDMT&IGD: Digital Multimedia and Computer Graphics;
  • PIE and MEDCOM: Ultrasound Scanners;
  • University of Roma 1 "Sapienza": Deep Submicron Back-end

Contact person: Pier Stanislao Paolucci – SHAPES Coordinator – ATMEL Roma Technology Director and INFN Roma (part-time) Permanent Staff Researcher for e-mail use pier.paolucci"upon"roma1.infn.it or pier.paolucci"upon"atmel.com

Europan IST Grant

SHAPES: Scalable Software Hardware Architecture Platform for Embedded Systems is a European Integrated Project funded under IST Future Emerging Technologies –Advanced Computing Architecture. Shapes Project started on January 2006.


Topic attachments
I Attachment Action Size Date Who Comment
PDFpdf Paolucci_Diopsis_SHAPES_MPSOC06.pdf manage 2424.0 K 2006-09-05 - 14:45 PierPaolucci First public SHAPES presentation at the MPSOC'06 conference (August 2006, Estes Park, Colorado)
PDFpdf shapes_codes_isss_2006_paper.pdf manage 421.1 K 2006-12-07 - 22:52 PierPaolucci codes_isss_2006_paper
Topic revision: r33 - 2010-08-05 - 12:17:52 - TWikiAdminUser
 
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