{"id":330,"date":"2019-02-18T11:00:35","date_gmt":"2019-02-18T11:00:35","guid":{"rendered":"https:\/\/wordpress.ape\/?page_id=330"},"modified":"2019-04-12T15:06:39","modified_gmt":"2019-04-12T15:06:39","slug":"talks","status":"publish","type":"page","link":"https:\/\/apegate.roma1.infn.it\/?page_id=330","title":{"rendered":"Talks"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"330\" class=\"elementor elementor-330 elementor-bc-flex-widget\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-2d0500c elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"2d0500c\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-308571b\" data-id=\"308571b\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-e4089ff elementor-widget elementor-widget-heading\" data-id=\"e4089ff\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">TALK<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-675a3bd elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"675a3bd\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-de4ede7\" data-id=\"de4ede7\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-835d787 elementor-widget elementor-widget-accordion\" data-id=\"835d787\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"accordion.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-accordion\">\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1371\" class=\"elementor-tab-title\" data-tab=\"1\" role=\"button\" aria-controls=\"elementor-tab-content-1371\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">APEnet<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1371\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"1\" role=\"region\" aria-labelledby=\"elementor-tab-title-1371\"><ul><li>M. Martinelli,<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">\u00a0&#8220;<\/span><b style=\"font-style: inherit;\">Hardware and Software Design of FPGA-\u00ad\u2010<\/b><b style=\"font-style: inherit;\">based PCIe Gen3 interface for APENet+\u00a0<b style=\"font-style: inherit;\">network interconnect system<\/b><\/b>&#8220;, CHEP 2015, 20 April 2015, Okinawa, Japan,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2015_apenet.pdf\">chep2015_apenet<\/a>\u00a0<\/li><li>R. Ammendola, &#8220;<b style=\"font-style: inherit;\">LO|FA|MO:Fault Detection and Systemic Awareness for\u00a0<b style=\"font-style: inherit;\">the QUonG computing system<\/b><\/b>&#8220;, SRDS 2014, 6 &#8211; 9 October 2014, Nara, Japan,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/srds2014_apenet.pdf\">srds2014_apenet<\/a>\u00a0<\/li><li>R. Ammendola, &#8220;<b style=\"font-style: inherit;\">Virtual-to-Physical Address Translation for an\u00a0<\/b><b style=\"font-style: inherit;\">FPGA-based Interconnect with Host and GPU Remote\u00a0<b style=\"font-style: inherit;\">DMA Capabilities<\/b><\/b>&#8220;, FPT 2013, 9 &#8211; 13 December\u00a0 2013, Kyoto, Japan,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/fpt2013_apenet.pdf\">fpt2013_apenet<\/a><\/li><li>O. Frezza, &#8220;<span style=\"font-size: 15px; font-style: normal;\"><b>Design and implementation of a modular, low latency, fault-aware, FPGA-based Network Interface<\/b>&#8220;, ReConFig 2013, 9 December 2013, Cancun, Mexico,\u00a0<\/span><a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/reconfig2013_apenet.pdf\">reconfig2013_apenet<\/a><\/li><li>A. Biagioni, &#8220;<b>APEnet+ 34 Gbps Data Transmission System and\u00a0Custom Transmission Logic<\/b>&#8220;, TWEPP 2013, 23 &#8211; 27 September 2013, Perugia, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/twepp2013_apenet.pdf\">twepp2013_apenet<\/a><\/li><li>D. Rossetti, &#8220;<b>GPU peer-to-peer techniques applied to a cluster interconnect<\/b>&#8220;, CASS 2013, 20 &#8211; 24 May 2013, Boston, Massachusetts,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/cass2013_apenet.pdf\">cass2013_apenet<\/a><\/li><li>P. Vicini, &#8220;<b>Analysis of performance improvements for host and GPU interface of the APENet+ 3D Torus network<\/b>&#8220;, ACAT 2013, 16 &#8211; 21 May 2013, Bejing, China,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/acat2013_apenet.pdf\">acat2013_apenet<\/a><\/li><li>D. Rossetti, &#8220;<b>Breadth First Search on APEnet+<\/b>&#8220;, Workshop on Irregular Application at SC12, 10 &#8211; 16 November 2012, Sal Lake City, Utah,\u00a0<\/li><li>D. Rossetti, &#8220;<b>Leveraging NVIDIA GPUDirect on APEnet+ 3D Torus Cluster Interconnect<\/b>&#8220;, GTC 2012, 14-17 May, San Jose, California,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/gtc2012_apenet.pdf\">gtc2012_apenet<\/a>\u00a0\u00a0<\/li><li>D. Rossetti, &#8220;<b>Remote Direct Memory Access Between NVIDIA GPUs with the APEnet 3D Torus Interconnect<\/b>&#8220;, Nvidia Booth at SC11, 14-17 November, Seattle, Washington,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/sc11_apenet.pdf\">sc11_apenet<\/a><\/li><li>P. Vicini, &#8220;<b>QUonG: a GPU-based parallel processor system for scientific computing<\/b>&#8220;, SM&amp;FT 2011, 18 September 2011, Bari, Italy<\/li><li style=\"font-size: 15px;\">P. Vicini, &#8220;<span style=\"font-weight: bold;\">QUonG: a GPU-based parallel processor system for scientific computing<\/span>&#8220;, SAAHPC 2011, 19-20 July 2011, Knoxville, Tennessee<\/li><li>D. Rossetti, &#8220;<b>Status of the APEnet+ project<\/b>&#8220;, Lattice 2011, 10-16 July, Ferrara, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/lattice11_rossetti.pdf\">lattice11_rossetti<\/a><\/li><li style=\"font-size: 15px;\">R. Ammendola, &#8220;<span style=\"font-weight: bold;\">APENet+: a 3D Toroidal Network Enabling PetaFlops Scale Lattice QCD Simulations on Commodity Clusters<\/span>&#8220;, Lattice 2010, 18 June, Villasimius, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/lattice10_ammendola.pdf\">lattice10_ammendola<\/a><\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1372\" class=\"elementor-tab-title\" data-tab=\"2\" role=\"button\" aria-controls=\"elementor-tab-content-1372\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">NaNet<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1372\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"2\" role=\"region\" aria-labelledby=\"elementor-tab-title-1372\"><ul><li style=\"font-size: 15px;\">P. Cretaro,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><span style=\"font-weight: bold;\">NaNet : a reconfigurable PCIe Network Interface Card Architecture for Real-time distributed heterogenous stream processing in the NA62 Low Level Trigger<\/span>&#8220;, TWEPP 2018, 17-21 September 2018, Antwerp, Belgium,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/twepp2018_nanet.pdf\">twepp2018_nanet<\/a><\/li><li>A. Lonardo,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><b>The NaNet Project: Real-time Distributed Heterogeneous Stream Processing for the NA62 Low Level Trigger<\/b>&#8220;, CHEP 2018, 9-13 July 2018, Sofia, Bulgaria,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2018_nanet.pdf\">chep2018_nanet<\/a><\/li><li>L. Pontisso,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><b>Real-time heterogeneous stream processing with NaNet in the NA62 experiment<\/b>&#8220;, ACAT 2017, 21-25 August 2017, Seattle, Washington,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/acat2017_nanet.pdf\">acat2017_nanet<\/a><\/li><li>A. Biagioni, &#8220;<b>NaNet: a configurable Network Interface Card for Trigger and DAQ Systems<\/b>&#8220;, CHEP 2016, 10-14 October 2016, San Francisco, California,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2016_nanet.pdf\">chep2016_nanet<\/a>\u00a0\u00a0<\/li><li>A. Biagioni, &#8220;<span style=\"font-weight: bold; font-size: 15px;\">NaNet: a Configurable\u00a0<span style=\"font-weight: bold;\">Network Interface Card for Trigger and DAQ Systems<\/span><\/span><span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;, GPU 2016, 26-28 September 2016, Roma, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/gpu2016_nanet.pdf\">gpu2016_nanet<\/a>\u00a0<\/span><\/li><li>A. Biagioni, &#8220;<b>Reconfigurable PCI Express cards for low-latency data transport in HEP experiments<\/b>&#8220;, IFAE 2016, 30 March &#8211; 1 April 2016, Genova, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/ifae2016_nanet.pdf\">ifae2016_nanet<\/a>\u00a0<\/li><li>A. Biagioni, &#8220;<b>NaNet3: the on-shore readout and slow-control board for the KM3NeT-IT underwater neutrino telescope<\/b>&#8220;, VLVnT 2015, 14 &#8211; 16 September 2015, Roma, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/vlvnt2015_nanet.pdf\">vlvnt2015_nanet<\/a><\/li><li>A. Lonardo, &#8220;<b style=\"font-style: inherit;\">A FPGA-based Network Interface Card with GPUDirect\u00a0<\/b><b style=\"font-style: inherit;\">enabling real-time GPU\u00a0computing in HEP experiments<\/b>&#8220;, GPU 2014, 15 &#8211; 17 September 2014, Roma, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/gpu2014_nanet.pdf\">gpu2014_nanet<\/a><\/li><li style=\"font-size: 15px;\">P. Vicini, &#8220;<b>NaNet: a Low Latency, Real-time, Multi-Standard network Interface Card with GPUDirect features<\/b>&#8220;, RT 2014, 26 &#8211; 30 May 2014, Osaka, Japan,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/rt2014_nanet.pdf\">rt2014_nanet<\/a>\u00a0<\/li><li>A. Lonardo, &#8220;<b>NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems<\/b>&#8220;, CHEP 2013,\u00a0 15 October 2013, Amsterdam, The Netherlands,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2013_nanet.pdf\">chep2013_nanet<\/a><\/li><li>A. Lonardo, &#8220;<b>Building a Low-latency, Real-time, GPU-based Stream Processing System<\/b>&#8220;, GTC 2013,\u00a0 20 March 2013, San Jose, California,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/gtc2013_nanet.pdf\">gtc2013_nanet<\/a><\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1373\" class=\"elementor-tab-title\" data-tab=\"3\" role=\"button\" aria-controls=\"elementor-tab-content-1373\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">Human Brain Project<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1373\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"3\" role=\"region\" aria-labelledby=\"elementor-tab-title-1373\"><ul><li style=\"font-size: 15px; font-style: normal; font-weight: 400;\">P. S. Paolucci, &#8220;<span style=\"font-weight: bold; font-size: 15px; font-style: normal;\">Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems<\/span>&#8220;, PDP 2019, 13-15 February 2019, Pavia, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"http:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/04\/pdp2019_hbp.pdf\">pdp2019_hbp<\/a><\/li><li style=\"font-size: 15px; font-style: normal; font-weight: 400;\"><span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">P. S. Paolucci<\/span>, &#8220;<span style=\"font-weight: bold; font-size: 15px; font-style: normal;\">Gaussian and Exponential Lateral Connectivity on Distributed Spiking Network Simulation<\/span>&#8220;,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">PDP 2018<\/span>, 12-15 March 2018, Cambridge, UK,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"http:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/04\/pdp2018_hbp.pdf\">pdp2018_hbp<\/a><\/li><li style=\"font-size: 15px; font-style: normal; font-weight: 400;\">A. Biagioni, &#8220;<span style=\"font-weight: bold;\"><span style=\"font-weight: bold; font-size: 15px; font-style: normal;\">The brain on low power architectures<\/span><\/span>&#8220;, ParCo 2017, 12-15 September 2017, Bologna, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/parco2017_hbp.pdf\">parco2017_hbp<\/a><\/li><li>E. Pastorelli, &#8220;<b>Simulations of Cortical Slow Waves and Transition toward Awake States<\/b>&#8220;, NEST 2016, 3 &#8211; 4\u00a0 November 2016, Karlsruhe, Germany,\u00a0<a href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/nest2016_hbp.pdf\" target=\"_blank\" rel=\"noopener\">nest2016_hbp<\/a><\/li><li style=\"font-size: 15px; font-style: normal;\">F. Simula, &#8220;<b>Distributed simulation of Polychronous and plastic Spiking Neural Networks: experiments with GPUs<\/b>&#8220;, GPU 2014, 15-17 September 2014, Roma, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/gpu2014_hbp.pdf\">gpu2014_hbp<\/a><\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1374\" class=\"elementor-tab-title\" data-tab=\"4\" role=\"button\" aria-controls=\"elementor-tab-content-1374\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">ExaNeSt<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1374\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"4\" role=\"region\" aria-labelledby=\"elementor-tab-title-1374\"><ul><li>P. Vicini,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><b style=\"font-style: inherit;\">Large scale low power architectures computing system:\u00a0<b style=\"font-style: inherit;\">status of ExaNeSt and EuroExa projects<\/b><\/b>&#8220;, ParCo 2017, 13 September 2017, Bologna, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/parco2017_exanest.pdf\">parco2017_exanest<\/a>\u00a0\u00a0 \u00a0\u00a0<\/li><li>A. Biagioni, &#8220;<b style=\"font-style: inherit;\">Low latency network and\u00a0<b style=\"font-style: inherit;\">distributed storage for next generation HPC systems: the ExaNeSt project<\/b><\/b>&#8220;, CHEP 2016, 10-14 October 2016, San Francisco, California,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2016_exanest.pdf\">chep2016_exanest<\/a>\u00a0\u00a0<\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1375\" class=\"elementor-tab-title\" data-tab=\"5\" role=\"button\" aria-controls=\"elementor-tab-content-1375\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">EURETILE<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1375\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"5\" role=\"region\" aria-labelledby=\"elementor-tab-title-1375\"><ul><li style=\"font-size: 15px; font-style: normal; font-weight: 400;\">A. Biagioni, &#8220;<span style=\"font-weight: bold;\">The EURETILE hardware experimental platform<\/span>&#8220;, CASTNESS 2013, 28 June 2013, Barcelona, Spain,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/castness2013_euretile_hw.pdf\">castness2013_euretile_hw<\/a>\u00a0<\/li><li>L. Tosoratto,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><b>Fault and Critical Event Awareness: a no-single-point-of-failure approach for distributed systems<\/b>&#8220;, CASTNESS 2013, 28 June 2013,\u00a0 Barcelona, Spain\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/castness2013_euretile_lofamo.pdf\">castness2013_euretile_lofamo<\/a>\u00a0<\/li><li>P. Vicini, &#8220;<b>Peer-to-peer GPGPU-APENet+ connectivity on HPC EURETILE platform<\/b>&#8220;, CASTNESS 2012, 26 January 2012, Paris, France,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/castness2012_euretile.pdf\">castness2012_euretile<\/a><\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1376\" class=\"elementor-tab-title\" data-tab=\"6\" role=\"button\" aria-controls=\"elementor-tab-content-1376\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">GAP<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1376\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"6\" role=\"region\" aria-labelledby=\"elementor-tab-title-1376\"><ul><li style=\"font-size: 15px;\">L. Pontisso,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><span style=\"font-size: 15px; font-weight: bold;\">Graphics Processors for HEP trigger systems<\/span>&#8220;, VCI 2016, 15 &#8211; 19 February 2016, Vienna, Austria,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/vci2016_gap.pdf\">vci2016_gap<\/a><\/li><li>P. Vicini, &#8220;<b>GPU for Real Time processing in HEP trigger systems<\/b>&#8220;, ACAT 2013, 18 May 2013, Bejing, China,\u00a0<\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-1d5c32a elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"1d5c32a\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-3aba576\" data-id=\"3aba576\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-7e3d4eb elementor-widget elementor-widget-spacer\" data-id=\"7e3d4eb\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"spacer.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-spacer\">\n\t\t\t<div class=\"elementor-spacer-inner\"><\/div>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-aafbf4f elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"aafbf4f\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-54510a3\" data-id=\"54510a3\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-8979c23 elementor-widget elementor-widget-heading\" data-id=\"8979c23\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">POSTER<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-11ae534 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"11ae534\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-9c4188a\" data-id=\"9c4188a\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-1022853 elementor-widget elementor-widget-accordion\" data-id=\"1022853\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"accordion.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-accordion\">\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1691\" class=\"elementor-tab-title\" data-tab=\"1\" role=\"button\" aria-controls=\"elementor-tab-content-1691\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">APEnet<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1691\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"1\" role=\"region\" aria-labelledby=\"elementor-tab-title-1691\"><ul><li>A. Biagioni, &#8220;<b>Latest generation interconnect\u00a0technologies in APEnet+ networking infrastructure<\/b>&#8220;, CHEP 2016, 10-14 October 2016, San Francisco, California,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2016_apenet.pdf\">chep2016_apenet<\/a>\u00a0<\/li><li style=\"font-size: 15px;\">L. Tosoratto, &#8220;<span style=\"font-size: 15px; font-weight: bold;\">Architectural improvements and Technological Enhancements for the APEnet+ Interconnect System\u00a0<\/span>&#8221; TWEPP 2014, 22-26 September 2014, Aix En Provence, France,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/twepp2014_apenet.pdf\">twepp2014_apenet<\/a><\/li><li>A. Biagioni, &#8220;<b>Evolution of FPGA-based network acceleration for GPUs<\/b>&#8220;, GPU 2014, 15-17 September 2014, Roma, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/gpu2014_apenet.pdf\">gpu2014_apenet<\/a><\/li><li>A. Lonardo, &#8220;<b>Architectural improvements and 28nm FPGA implementation of the\u00a0APEnet+ 3D Torus network for hybrid HPC systems<\/b>&#8220;, CHEP 2013, 14-18 October 2018, Amsterdam, The Netherlands,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2013_apenet.pdf\">chep2013_apenet<\/a>\u00a0<\/li><li>R. Ammendola, &#8220;<b>APEnet+: a 12&#215;34 Gbps data transmission system with FPGAs embedded transceivers and QSFP+ modules<\/b>&#8220;, NSS\/MIC 2012, 29 October &#8211; 3 November 2012, Anaheim, California\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/nss2012_apenet.pdf\">nss2012_apenet<\/a><\/li><li>L. Tosoratto, &#8220;<b>APEnet+: a 3D Torus network optimized for GPU-based HPC Systems<\/b>&#8220;, CHEP 2012, 21 &#8211; 25 May 2012, New York,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2012_apenet.pdf\">chep2012_apenet<\/a><\/li><li style=\"font-size: 15px;\">F. Lo Cicero,\u00a0<span style=\"font-size: 15px; font-weight: bold;\">&#8220;<\/span><span style=\"font-weight: bold;\">apeNET+: High Bandwidth 3D Torus Direct Network for PetaFLOPS\u00a0<span style=\"font-weight: bold;\">Scale Commodity Clusters<\/span><\/span>&#8220;, CHEP 2010, 18 &#8211; 22 October 2010, Taipei, Taiwan,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2010_apenet.pdf\">chep2010_apenet<\/a><\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1692\" class=\"elementor-tab-title\" data-tab=\"2\" role=\"button\" aria-controls=\"elementor-tab-content-1692\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">NaNet<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1692\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"2\" role=\"region\" aria-labelledby=\"elementor-tab-title-1692\"><ul><li style=\"font-size: 15px;\">P. Cretaro, &#8220;<b>Development of Network Interface Cards for TRIDAQ Systems with the NaNet Framework<\/b>&#8221; TWEPP 2016, 26 &#8211; 30 September 2016, Padova, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/twepp2016_nanet.pdf\">twepp2016_nanet<\/a><\/li><li>M. Martinelli, &#8220;<b style=\"font-style: inherit;\">FPGA-based Network Interface Cards\u00a0<b style=\"font-style: inherit;\">Implementing Real-time Data Transport for HEP Experiments<\/b><\/b>&#8221; RT2016, 5-10 June 2016, Padova, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/rt2016_nanet.pdf\">rt2016_nanet<\/a><\/li><li>M. Martinelli &#8220;<b>NaNet: Design of FPGA-Based Network Interface Cards for Real-Time Trigger and Data Acquisition Systems in HEP Experiments<\/b>.&#8221; NSS\/MIC 2015, 1-7 November 2015, San Diego, California,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/nss2015_nanet.pdf\">nss2015_nanet<\/a><\/li><li>A. Biagioni, &#8220;<b>NaNet-10: a 10GbE Network Interface Card for\u00a0the GPU-based low-level Trigger of the NA62 RICH Detector<\/b>&#8221; TWEPP 2015, 28 September &#8211; 2 October 2015, Lisbon, Portugal,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/twepp2015_nanet.pdf\">twepp2015_nanet<\/a><\/li><li>A. Biagioni, &#8220;<b>A multi-port 10GbE PCIe NIC featuring UDP offload and GPUDirect capabilities\u00a0<\/b>&#8221; CHEP 2015, 13-17 April 2015, Okinawa, Japan,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2015_nanet.pdf\">chep2015_nanet<\/a><\/li><li>L. Tosoratto, &#8220;<b style=\"font-style: inherit;\">NaNet: a Configurable NIC Bridging the Gap Between HPC\u00a0<b style=\"font-style: inherit;\">and Real-time HEP GPU Computing<\/b><\/b>&#8221; TWEPP 2014, 22-26 September 2014, Aix En Provence, France,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/twepp2014_nanet.pdf\">twepp2014_nanet<\/a><\/li><li>A. Biagioni, &#8220;<b>Development of a GPU aware NIC: from HPC to HEP experiments\u00a0<\/b>&#8221; GTC 2014, 24-27 March 2014, San Jose, California,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/gtc2014_nanet.pdf\">gtc2014_nanet<\/a><\/li><li>A. Biagioni, &#8220;<b>NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs\u00a0<\/b>&#8221; TWEPP 2013, 23-27 September 2013, Perugia, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/twepp2013_nanet.pdf\">twepp2013_nanet<\/a><\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1693\" class=\"elementor-tab-title\" data-tab=\"3\" role=\"button\" aria-controls=\"elementor-tab-content-1693\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">Human Brain Project<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1693\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"3\" role=\"region\" aria-labelledby=\"elementor-tab-title-1693\"><ul style=\"font-size: 15px; font-style: normal;\"><li style=\"font-size: 15px;\">E. Pastorelli et Al.,\u00a0\u201c<b>Distributed large scale simulation of synchronour slow-wave \/ asynchronous awake-like cortical activity<\/b>,\u201d\u00a0NEST Conference 2017, 19-20 December 2017, J\u00fclich, Germany,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/nest2017_hbp.pdf\">nest2017_hbp<\/a><\/li><li style=\"font-size: 15px;\"><span style=\"font-weight: 400;\">E. Pastorelli et Al.,\u00a0\u201c<\/span><b>Distributed large scale simulation of synchronour slow-wave \/ asynchronous awake-like cortical activity<\/b>,\u201d\u00a05th annual Human Brain Project Summit, 17-20 October 2017,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/5hbp_hbp.pdf\">5hbp_hbp<\/a>\u00a0<\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1694\" class=\"elementor-tab-title\" data-tab=\"4\" role=\"button\" aria-controls=\"elementor-tab-content-1694\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">ExaNeSt<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1694\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"4\" role=\"region\" aria-labelledby=\"elementor-tab-title-1694\"><ul><li>A. Lonardo,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><b style=\"font-style: inherit;\">Low power, large scale HPC platforms for scientific and engineering applications:\u00a0<b style=\"font-style: inherit;\">status of ExaNeSt and EuroExa H2020 FETHPC projects<\/b><\/b>&#8220;, CHEP 2018, 9 &#8211; 13 July 2018, Sofia, Bulgaria,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2018_exanest.pdf\">chep2018_exanest<\/a><\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1695\" class=\"elementor-tab-title\" data-tab=\"5\" role=\"button\" aria-controls=\"elementor-tab-content-1695\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">EURETILE<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1695\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"5\" role=\"region\" aria-labelledby=\"elementor-tab-title-1695\"><ul><li>L. Tosoratto,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<b style=\"font-style: inherit;\">EURETILE: Unified Networking Infrastructure for Embedded and HPC many-tile platforms<\/b><\/span>&#8220;, HIPEAC12, 28 January 2012, Paris, France,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/hipeac2012_euretile.pdf\">hipeac2012_euretile<\/a><\/li><li>P. S. Paolucci,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><b>Brain Simulation Benchmark: Inspiring and benchmarking the scalability and fault-tolerance of future many-tile systems<\/b>&#8220;, HIPEAC12, 28 January 2012, Paris, France,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/hipeac2012_euretile_hbp.pdf\">hipeac2012_euretile_hbp<\/a><\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t<div class=\"elementor-accordion-item\">\n\t\t\t\t\t<div id=\"elementor-tab-title-1696\" class=\"elementor-tab-title\" data-tab=\"6\" role=\"button\" aria-controls=\"elementor-tab-content-1696\" aria-expanded=\"false\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t<span class=\"elementor-accordion-icon elementor-accordion-icon-left\" aria-hidden=\"true\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-closed fa fa-plus\"><\/i>\n\t\t\t\t\t\t\t\t<i class=\"elementor-accordion-icon-opened fa fa-minus\"><\/i>\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/span>\n\t\t\t\t\t\t\t\t\t\t\t\t<a class=\"elementor-accordion-title\" tabindex=\"0\">GAP<\/a>\n\t\t\t\t\t<\/div>\n\t\t\t\t\t<div id=\"elementor-tab-content-1696\" class=\"elementor-tab-content elementor-clearfix\" data-tab=\"6\" role=\"region\" aria-labelledby=\"elementor-tab-title-1696\"><ul><li style=\"font-size: 15px;\"><span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">M. Martinelli,\u00a0<\/span><span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><b>GPU for triggering in HEP experiments<\/b>&#8220;, RT 2016, 10 June 2016, Padova, Italy,\u00a0<a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/rt2016_gap.pdf\">rt2016_gap<\/a><\/li><li style=\"font-size: 15px;\">A. Lonardo,\u00a0<span style=\"font-size: 15px; font-style: normal; font-weight: 400;\">&#8220;<\/span><b style=\"font-style: inherit;\">GPU for Real Time processing in HEP trigger system<\/b><span style=\"font-size: 15px;\">&#8220;, CHEP 2013, 14-18 October 2013, Amsterdam, The Netherlands,\u00a0<\/span><a style=\"font-size: 15px; font-style: normal; font-weight: 400; background-color: #ffffff;\" href=\"https:\/\/apegate.roma1.infn.it\/wp-content\/uploads\/2019\/02\/chep2013_gap.pdf\">chep2013_gap<\/a><\/li><\/ul><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>TALK APEnet M. Martinelli,\u00a0&#8220;Hardware and Software Design of FPGA-\u00ad\u2010based PCIe Gen3 interface for APENet+\u00a0network interconnect system&#8220;, CHEP 2015, 20 April 2015, Okinawa, Japan,\u00a0chep2015_apenet\u00a0 R. Ammendola, &#8220;LO|FA|MO:Fault Detection and Systemic Awareness for\u00a0the QUonG computing system&#8220;, SRDS 2014, 6 &#8211; 9 October 2014, Nara, Japan,\u00a0srds2014_apenet\u00a0 R. Ammendola, &#8220;Virtual-to-Physical Address Translation for an\u00a0FPGA-based Interconnect with Host and GPU [&hellip;]<\/p>\n","protected":false},"author":5,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_seopress_robots_primary_cat":"","_seopress_titles_title":"","_seopress_titles_desc":"","_seopress_robots_index":"","_exactmetrics_skip_tracking":false,"_exactmetrics_sitenote_active":false,"_exactmetrics_sitenote_note":"","_exactmetrics_sitenote_category":0,"site-sidebar-layout":"default","site-content-layout":"default","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"disabled","ast-breadcrumbs-content":"","ast-featured-img":"disabled","footer-sml-layout":"","ast-disable-related-posts":"","theme-transparent-header-meta":"default","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"class_list":["post-330","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/apegate.roma1.infn.it\/index.php?rest_route=\/wp\/v2\/pages\/330","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/apegate.roma1.infn.it\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/apegate.roma1.infn.it\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/apegate.roma1.infn.it\/index.php?rest_route=\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/apegate.roma1.infn.it\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=330"}],"version-history":[{"count":79,"href":"https:\/\/apegate.roma1.infn.it\/index.php?rest_route=\/wp\/v2\/pages\/330\/revisions"}],"predecessor-version":[{"id":1204,"href":"https:\/\/apegate.roma1.infn.it\/index.php?rest_route=\/wp\/v2\/pages\/330\/revisions\/1204"}],"wp:attachment":[{"href":"https:\/\/apegate.roma1.infn.it\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=330"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}