Difference between revisions of "APEmille project"
From APEWiki
Jump to navigationJump to search| Line 7: | Line 7: | ||
| − | # | + | # Architectural Overview |
| − | # | + | # Topology |
| − | # | + | # Processing Board |
| − | # | + | # Processing Node |
| − | # | + | # Tmille |
| − | # | + | # Jmille |
| − | # | + | # Cmille |
| − | # | + | # PB interconnections |
| − | # | + | # Memory |
| − | # | + | # Software |
Revision as of 08:43, 5 October 2006
APEmille
A PARALLEL PROCESSOR IN THE TERAFLOPS RANGE
This document describes APEmille, a 3-D SIMD scalable parallel processor in the Teraflop range. This machine is very efficient for LGT simulations as well as for a broader class of numeric applications requiring massive intensive floating point computations.
- Architectural Overview
- Topology
- Processing Board
- Processing Node
- Tmille
- Jmille
- Cmille
- PB interconnections
- Memory
- Software
