Difference between revisions of "Overview of the APE Architecture"
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Revision as of 10:45, 9 June 2011
The APE machines are massively parallel 3D arrays of custom computing nodes with periodic boundary conditions. Four generations of APE supercomputing engines have been characterized by impressive value of sustained performances, performance/volume, performance/power and performance/price ratios. The APE group made extensive use of VLSI design, designing VLIW processor architectures with native implementation of the complex type operator performing the AxB+C operation and large multi-port register files for high bandwidth with the arithmetic block. The interconnection system is optimized for low-latency, high bandwidth nearest-neighbours communication. The result is a dense system, based on a reliable and safe HW solution. It has been necessary to develop a custom mechanics for wide integration of cheap systems with very low cost of maintenance.
APE | APE100 | APEmille | APEnext | |
---|---|---|---|---|
Year | 1984-1988 | 1989-1993 | 1994-1999 | 2000-2005 |
Number of processors | 16 | 2048 | 2048 | 4096 |
Topology | Flexible 1D | Next Neighbour 3D | Flexible 3D | Flexible 3D |
Total Memory | 256 MB | 8 GB | 64 GB | 1 TB |
Clock | 8 MHz | 25 MHz | 66 MHz | 200 Mhz |
Peak Processing Power | 1 GFlops | 100 GFlops | 1 TFlops | 7 TFlops |
Architecture Design Tradeoffs
As pointed before one of the most critical issue for the design of the next generations of high performance numerical applications will be the power dissipation. A typical figure is the power dissipation per unit area. The following picture illustrates the efficiency of the approach adopted by INFN: 100px