TALK
- M. Martinelli, “Hardware and Software Design of FPGA-‐based PCIe Gen3 interface for APENet+ network interconnect system“, CHEP 2015, 20 April 2015, Okinawa, Japan, chep2015_apenet
- R. Ammendola, “LO|FA|MO:Fault Detection and Systemic Awareness for the QUonG computing system“, SRDS 2014, 6 – 9 October 2014, Nara, Japan, srds2014_apenet
- R. Ammendola, “Virtual-to-Physical Address Translation for an FPGA-based Interconnect with Host and GPU Remote DMA Capabilities“, FPT 2013, 9 – 13 December 2013, Kyoto, Japan, fpt2013_apenet
- O. Frezza, “Design and implementation of a modular, low latency, fault-aware, FPGA-based Network Interface“, ReConFig 2013, 9 December 2013, Cancun, Mexico, reconfig2013_apenet
- A. Biagioni, “APEnet+ 34 Gbps Data Transmission System and Custom Transmission Logic“, TWEPP 2013, 23 – 27 September 2013, Perugia, Italy, twepp2013_apenet
- D. Rossetti, “GPU peer-to-peer techniques applied to a cluster interconnect“, CASS 2013, 20 – 24 May 2013, Boston, Massachusetts, cass2013_apenet
- P. Vicini, “Analysis of performance improvements for host and GPU interface of the APENet+ 3D Torus network“, ACAT 2013, 16 – 21 May 2013, Bejing, China, acat2013_apenet
- D. Rossetti, “Breadth First Search on APEnet+“, Workshop on Irregular Application at SC12, 10 – 16 November 2012, Sal Lake City, Utah,
- D. Rossetti, “Leveraging NVIDIA GPUDirect on APEnet+ 3D Torus Cluster Interconnect“, GTC 2012, 14-17 May, San Jose, California, gtc2012_apenet
- D. Rossetti, “Remote Direct Memory Access Between NVIDIA GPUs with the APEnet 3D Torus Interconnect“, Nvidia Booth at SC11, 14-17 November, Seattle, Washington, sc11_apenet
- P. Vicini, “QUonG: a GPU-based parallel processor system for scientific computing“, SM&FT 2011, 18 September 2011, Bari, Italy
- P. Vicini, “QUonG: a GPU-based parallel processor system for scientific computing“, SAAHPC 2011, 19-20 July 2011, Knoxville, Tennessee
- D. Rossetti, “Status of the APEnet+ project“, Lattice 2011, 10-16 July, Ferrara, Italy, lattice11_rossetti
- R. Ammendola, “APENet+: a 3D Toroidal Network Enabling PetaFlops Scale Lattice QCD Simulations on Commodity Clusters“, Lattice 2010, 18 June, Villasimius, Italy, lattice10_ammendola
- P. Cretaro, “NaNet : a reconfigurable PCIe Network Interface Card Architecture for Real-time distributed heterogenous stream processing in the NA62 Low Level Trigger“, TWEPP 2018, 17-21 September 2018, Antwerp, Belgium, twepp2018_nanet
- A. Lonardo, “The NaNet Project: Real-time Distributed Heterogeneous Stream Processing for the NA62 Low Level Trigger“, CHEP 2018, 9-13 July 2018, Sofia, Bulgaria, chep2018_nanet
- L. Pontisso, “Real-time heterogeneous stream processing with NaNet in the NA62 experiment“, ACAT 2017, 21-25 August 2017, Seattle, Washington, acat2017_nanet
- A. Biagioni, “NaNet: a configurable Network Interface Card for Trigger and DAQ Systems“, CHEP 2016, 10-14 October 2016, San Francisco, California, chep2016_nanet
- A. Biagioni, “NaNet: a Configurable Network Interface Card for Trigger and DAQ Systems“, GPU 2016, 26-28 September 2016, Roma, Italy, gpu2016_nanet
- A. Biagioni, “Reconfigurable PCI Express cards for low-latency data transport in HEP experiments“, IFAE 2016, 30 March – 1 April 2016, Genova, Italy, ifae2016_nanet
- A. Biagioni, “NaNet3: the on-shore readout and slow-control board for the KM3NeT-IT underwater neutrino telescope“, VLVnT 2015, 14 – 16 September 2015, Roma, Italy, vlvnt2015_nanet
- A. Lonardo, “A FPGA-based Network Interface Card with GPUDirect enabling real-time GPU computing in HEP experiments“, GPU 2014, 15 – 17 September 2014, Roma, Italy, gpu2014_nanet
- P. Vicini, “NaNet: a Low Latency, Real-time, Multi-Standard network Interface Card with GPUDirect features“, RT 2014, 26 – 30 May 2014, Osaka, Japan, rt2014_nanet
- A. Lonardo, “NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems“, CHEP 2013, 15 October 2013, Amsterdam, The Netherlands, chep2013_nanet
- A. Lonardo, “Building a Low-latency, Real-time, GPU-based Stream Processing System“, GTC 2013, 20 March 2013, San Jose, California, gtc2013_nanet
- P. S. Paolucci, “Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems“, PDP 2019, 13-15 February 2019, Pavia, Italy, pdp2019_hbp
- P. S. Paolucci, “Gaussian and Exponential Lateral Connectivity on Distributed Spiking Network Simulation“, PDP 2018, 12-15 March 2018, Cambridge, UK, pdp2018_hbp
- A. Biagioni, “The brain on low power architectures“, ParCo 2017, 12-15 September 2017, Bologna, Italy, parco2017_hbp
- E. Pastorelli, “Simulations of Cortical Slow Waves and Transition toward Awake States“, NEST 2016, 3 – 4 November 2016, Karlsruhe, Germany, nest2016_hbp
- F. Simula, “Distributed simulation of Polychronous and plastic Spiking Neural Networks: experiments with GPUs“, GPU 2014, 15-17 September 2014, Roma, Italy, gpu2014_hbp
- P. Vicini, “Large scale low power architectures computing system: status of ExaNeSt and EuroExa projects“, ParCo 2017, 13 September 2017, Bologna, Italy, parco2017_exanest
- A. Biagioni, “Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project“, CHEP 2016, 10-14 October 2016, San Francisco, California, chep2016_exanest
- A. Biagioni, “The EURETILE hardware experimental platform“, CASTNESS 2013, 28 June 2013, Barcelona, Spain, castness2013_euretile_hw
- L. Tosoratto, “Fault and Critical Event Awareness: a no-single-point-of-failure approach for distributed systems“, CASTNESS 2013, 28 June 2013, Barcelona, Spain castness2013_euretile_lofamo
- P. Vicini, “Peer-to-peer GPGPU-APENet+ connectivity on HPC EURETILE platform“, CASTNESS 2012, 26 January 2012, Paris, France, castness2012_euretile
- L. Pontisso, “Graphics Processors for HEP trigger systems“, VCI 2016, 15 – 19 February 2016, Vienna, Austria, vci2016_gap
- P. Vicini, “GPU for Real Time processing in HEP trigger systems“, ACAT 2013, 18 May 2013, Bejing, China,
POSTER
- A. Biagioni, “Latest generation interconnect technologies in APEnet+ networking infrastructure“, CHEP 2016, 10-14 October 2016, San Francisco, California, chep2016_apenet
- L. Tosoratto, “Architectural improvements and Technological Enhancements for the APEnet+ Interconnect System ” TWEPP 2014, 22-26 September 2014, Aix En Provence, France, twepp2014_apenet
- A. Biagioni, “Evolution of FPGA-based network acceleration for GPUs“, GPU 2014, 15-17 September 2014, Roma, Italy, gpu2014_apenet
- A. Lonardo, “Architectural improvements and 28nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems“, CHEP 2013, 14-18 October 2018, Amsterdam, The Netherlands, chep2013_apenet
- R. Ammendola, “APEnet+: a 12×34 Gbps data transmission system with FPGAs embedded transceivers and QSFP+ modules“, NSS/MIC 2012, 29 October – 3 November 2012, Anaheim, California nss2012_apenet
- L. Tosoratto, “APEnet+: a 3D Torus network optimized for GPU-based HPC Systems“, CHEP 2012, 21 – 25 May 2012, New York, chep2012_apenet
- F. Lo Cicero, “apeNET+: High Bandwidth 3D Torus Direct Network for PetaFLOPS Scale Commodity Clusters“, CHEP 2010, 18 – 22 October 2010, Taipei, Taiwan, chep2010_apenet
- P. Cretaro, “Development of Network Interface Cards for TRIDAQ Systems with the NaNet Framework” TWEPP 2016, 26 – 30 September 2016, Padova, Italy, twepp2016_nanet
- M. Martinelli, “FPGA-based Network Interface Cards Implementing Real-time Data Transport for HEP Experiments” RT2016, 5-10 June 2016, Padova, Italy, rt2016_nanet
- M. Martinelli “NaNet: Design of FPGA-Based Network Interface Cards for Real-Time Trigger and Data Acquisition Systems in HEP Experiments.” NSS/MIC 2015, 1-7 November 2015, San Diego, California, nss2015_nanet
- A. Biagioni, “NaNet-10: a 10GbE Network Interface Card for the GPU-based low-level Trigger of the NA62 RICH Detector” TWEPP 2015, 28 September – 2 October 2015, Lisbon, Portugal, twepp2015_nanet
- A. Biagioni, “A multi-port 10GbE PCIe NIC featuring UDP offload and GPUDirect capabilities ” CHEP 2015, 13-17 April 2015, Okinawa, Japan, chep2015_nanet
- L. Tosoratto, “NaNet: a Configurable NIC Bridging the Gap Between HPC and Real-time HEP GPU Computing” TWEPP 2014, 22-26 September 2014, Aix En Provence, France, twepp2014_nanet
- A. Biagioni, “Development of a GPU aware NIC: from HPC to HEP experiments ” GTC 2014, 24-27 March 2014, San Jose, California, gtc2014_nanet
- A. Biagioni, “NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs ” TWEPP 2013, 23-27 September 2013, Perugia, Italy, twepp2013_nanet
- E. Pastorelli et Al., “Distributed large scale simulation of synchronour slow-wave / asynchronous awake-like cortical activity,” NEST Conference 2017, 19-20 December 2017, Jülich, Germany, nest2017_hbp
- E. Pastorelli et Al., “Distributed large scale simulation of synchronour slow-wave / asynchronous awake-like cortical activity,” 5th annual Human Brain Project Summit, 17-20 October 2017, 5hbp_hbp
- A. Lonardo, “Low power, large scale HPC platforms for scientific and engineering applications: status of ExaNeSt and EuroExa H2020 FETHPC projects“, CHEP 2018, 9 – 13 July 2018, Sofia, Bulgaria, chep2018_exanest
- L. Tosoratto, “EURETILE: Unified Networking Infrastructure for Embedded and HPC many-tile platforms“, HIPEAC12, 28 January 2012, Paris, France, hipeac2012_euretile
- P. S. Paolucci, “Brain Simulation Benchmark: Inspiring and benchmarking the scalability and fault-tolerance of future many-tile systems“, HIPEAC12, 28 January 2012, Paris, France, hipeac2012_euretile_hbp
- M. Martinelli, “GPU for triggering in HEP experiments“, RT 2016, 10 June 2016, Padova, Italy, rt2016_gap
- A. Lonardo, “GPU for Real Time processing in HEP trigger system“, CHEP 2013, 14-18 October 2013, Amsterdam, The Netherlands, chep2013_gap